Capacitive techniques to reduce noise in high speed interconnections

ABSTRACT

Structures, in various embodiments, are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. In an embodiment, a transmission line is disposed on a first layer of insulating material, where the first layer of insulating has a thickness equal to or less than 1.0 micrometer. The transmission line may be structured with a thickness and a width of approximately 1.0 micrometers. A second layer of insulating material is disposed on the transmission line.

CROSS REFERENCE TO RELATED APPLICATION

This application is a Divisional of U.S. Ser. No. 10/930,158 filed onAug. 31, 2004, which is a Divisional of U.S. Ser. No. 10/060,801 filedon Jan. 30, 2002. These applications are herein incorporated byreference.

FIELD OF THE INVENTION

The present invention relates to integrated circuit devices, and moreparticularly, to methods and structures using capacitive techniques toreduce noise in high speed interconnections.

BACKGROUND OF THE INVENTION

The metal lines over insulators and ground planes, or metal lines buriedin close proximity to dielectric insulators and used for integratedcircuit interconnects are in reality transmission lines or strip lines.The use of coaxial interconnection lines for interconnections throughthe substrate in CMOS integrated circuits can also be termedtransmission lines or strip lines. Interconnection lines on interposersor printed circuit boards can also be described as transmission lines.

The low characteristic impedance of any of these lines, transmission,strip lines or coaxial lines results in part from the low characteristicimpedance of free space, Zo=(μ₀/ε₀)^(1/2)=377 ohms, and in part from thedielectric material used for electrical insulation in the lines whichhas a higher dielectric permittivity than free space. Most commonly usedcoaxial lines have an impedance of 50 ohms or 75 ohms, it is difficultto achieve larger values. In the past these effects have not receivedmuch consideration on the integrated circuits themselves since thepropagation speed with oxide insulators is 15 cm/ns and switching speedson integrated circuits of the size of a centimeter have been slower than1/15 ns or 70 picoseconds. Transmission line effects only becomeimportant if the switching time is of the same order as the signalpropagation time. Switching times in CMOS circuits have been limited bythe ability to switch the capacitive loads of long lines and buffers,and charge these capacitances over large voltage swings to yield avoltage step signal.

Most current CMOS integrated circuit interconnections rely on thetransmission of a voltage step or signal from one location to another.FIG. 1 illustrates R-C limited, short high impedance interconnectionswith capacitive loads. The driver may simply be a CMOS inverter as shownin FIG. 1 and the receiver a simple CMOS amplifier, differentialamplifier, or comparator.

As shown in FIG. 1, the CMOS receiver presents a high impedancetermination or load to the interconnection line. This is problematic inthat:

(i) the switching time response or signal delay is determined mainly bythe ability of the driver to charge up the capacitance of the line andthe load capacitance,

(ii) the line is not terminated by its characteristic impedanceresulting in reflections and ringing,

(iii) large noise voltages may be induced on the signal transmissionline due to capacitive coupling and large voltage swing switching onadjacent lines, the noise voltage can be a large fraction of the signalvoltage.

The transmission of voltage step signals only works well if theinterconnection line is short so that the stray capacitance of the lineis small. Long lines result is slow switching speeds and excessive noisedue to capacitive coupling between lines.

FIG. 1 shows the commonly used signal interconnection in CMOS integratedcircuits, where voltage signals are transmitted from one location toanother. This is problematic in that the interconnection lines arenormally loaded with the capacitive input of the next CMOS stage and thelarge stray capacitance of the line itself. The response time isnormally slow due to the limited ability of the line drivers to supplythe large currents needed to charge these capacitances over largevoltage swings. These times are usually much larger than the signaltransmission time down the line so a lumped circuit model can be used tofind the signal delay, as shown in FIG. 1.

In the example here the output impedance of the source follower is1/gm=1000 ohms, and a line 0.1 cm long will have a capacitance of about0.2 pF if the dimensions of the line are about 1 micron by 1 micron andthe insulator or oxide thickness under the line is 1 micron. Thisresults in a time constant of 200 pS and it takes about 400 pS to chargethe line from 10% to 90% of the final voltage value. This is arelatively slow response.

Furthermore, if two interconnection wires are in close proximity thenthe voltage swing on one line can induce a large voltage swing or noisevoltage on the adjacent line as shown in FIG. 1. The noise voltage isjust determined by the capacitance ratios, or ratio of interwirecapacitance, Cint, to the capacitance of the interconnection wire, C.

In prior art these can be comparable, as shown, and depend on theinsulator thickness under the wires and the spacing between the wires.Therefore, the noise voltage can be a large fraction of the signalvoltage if the wires are in close proximity and far removed from thesubstrate by being over thick insulators. The emphasis in prior art hasalways been in trying to minimize the capacitance of the interconnectionline, C, by using thick insulators and low dielectric constantmaterials.

Thus, there is a need to provide a solution for these types of problemsfor CMOS-scaled integrated circuits. Due to the continued reduction inscaling and increases in frequency for transmission lines in integratedcircuits such solutions remain a difficult hurdle. For these and otherreasons there is a need to reduce noise in high speed interconnections.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the commonly used signal interconnection in CMOS integratedcircuits, where voltage signals are transmitted from one location toanother.

FIG. 2 illustrates one technique to minimize the interwire capacitance,Cint, by using an intermediate line at ground for shielding.

FIG. 3A illustrates signal transmission using correctly terminatedtransmission lines and current sense amplifiers, according to theteachings of the present invention.

FIG. 3B illustrates two interconnection lines in close proximity and theinterwire capacitance between these lines and the mutual inductancecoupling between the lines.

FIG. 4 is a perspective view illustrating a pair of neighboringtransmission lines above a conductive substrate, according to theteachings of the present invention.

FIG. 5 is a perspective view illustrating another embodiment for a pairof neighboring transmission lines above a conductive substrate,according to the teachings of present invention.

FIG. 6 is a schematic diagram for an interconnection on an integratedcircuit 600 according to the teachings of the present invention.

FIGS. 7A-7F illustrate an embodiment of a process of fabrication oftransmission lines in an integrated circuit according to the teachingsof the present invention.

FIGS. 8A-8F illustrate another embodiment of a process of fabrication oftransmission lines in an integrated circuit according to the teachingsof the present invention.

FIG. 9 is a block diagram which illustrates an embodiment of a systemusing line signaling according to teachings of the present invention.

FIG. 10 is a block diagram which illustrates another embodiment of asystem according to teaching of the present invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention.

The terms wafer and substrate used in the following description includeany structure having an exposed surface with which to form theintegrated circuit (IC) structure of the invention. The term substrateis understood to include semiconductor wafers. The term substrate isalso used to refer to semiconductor structures during processing, andmay include other layers that have been fabricated thereupon. Both waferand substrate include doped and undoped semiconductors, epitaxialsemiconductor layers supported by a base semiconductor or insulator, aswell as other semiconductor structures well known to one skilled in theart. The term conductor is understood to include semiconductors, and theterm insulator is defined to include any material that is lesselectrically conductive than the materials referred to as conductors.The following detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

One embodiment of the invention includes a method for formingtransmission lines in an integrated circuit. The method include forminga first layer of electrically conductive material on a substrate. Themethod includes forming a first layer of insulating material on thefirst layer of the electrically conductive material. The first layer hasa thickness of less than 1.0 micrometers (μm). A transmission line isformed on the first layer of insulating material. The transmission linehas a thickness and a width of approximately 1.0 micrometers. A secondlayer of insulating material is formed on the transmission line. And, asecond layer of electrically conductive material is formed on the secondlayer of insulating material.

FIG. 2 illustrates one technique to minimize the interwire capacitance,Cint, by using an intermediate line at ground for shielding. Thistechnique is disclosed in a co-pending application by a common inventor,Dr. Leonard Forbes, entitled “Novel Transmission Lines for CMOSIntegrated Circuits,” Ser. No. 09/364,199. The same is incorporatedherein by reference.

Also, as disclosed in issued U.S. Pat. No. 6,255,852 by Dr. LeonardForbes, entitled “Current Mode Interconnects on CMOS IntegratedCircuits,” low impedance transmission lines such as those which exist onCMOS integrated circuits are more amenable to signal currentinterconnections over longer interconnection lines. U.S. Pat. No.6,255,852 is incorporated herein by reference. These longerinterconnection lines may be on the CMOS integrated circuit itself, aninterconnection line between integrated circuits mounted in a module asfor instance a memory module, an interposer upon which these integratedcircuits are mounted, or on a printed circuit board upon which theintegrated circuits are mounted. If the line is terminated with a lowinput impedance current sense amplifier then the line can be regarded asa transmission line terminated with the characteristic impedance of theinterconnection line. This is advantageous in that:

(i) the signal delay depends only on the velocity of light on the lineand is easily predictable and reproducible, eliminating or allowing forcompensation for signal and/or clock skew,

(ii) there are no reflections at the receiving end of the line and thisminimizes ringing,

(iii) noise signals will be smaller due to weaker coupling between linesresulting in better signal to noise ratios, the noise current will onlybe a small fraction of the signal current. The transmission of currentsignals rather than voltage signals is more desirable at high speeds,and in high speed or high clock rate circuits over longerinterconnection lines. A CMOS circuit might for instance use acombination of techniques, conventional voltage signals over shortinterconnections with little coupling between lines and current signalsover longer interconnections and where lines might be in closeproximity.

FIG. 3A illustrates capacitive coupling between low impedance terminatedinterconnection lines. FIG. 3A illustrates signal transmission usingcorrectly terminated transmission lines and current sense amplifiers,such as those disclosed in issued U.S. Pat. No. 6,255,852 by Dr. LeonardForbes, entitled “Current Mode Interconnects on CMOS IntegratedCircuits.” The signal interconnection or transmission line is terminatedby the matching impedance of the current sense amplifier. This means theimpedance looking into the sending end of the transmission line willjust be the characteristic impedance of the line and the signal delaydown the line will just be the small propagation delay down the line.The response time of the source follower being used as a line driverwill be determined primarily by the longer rise time of the inputvoltage. This driver will supply a current whose rise time is basicallyjust that of the input voltage. This driver will then supply a signalcurrent whose rise time is basically just that of the input voltagesignal.

FIG. 3A also illustrates the coupling to another signal line in closeproximity, in this case the coupling will be both magnetic through theinduced magnetic fields and mutual inductance and capacitive coupling.The noise current induced will be shown to be only a fraction of thesignal current or the signal to noise ratio is high. Once received thissignal current is converted back to a signal voltage by the currentsense amplifier at the receiving end of the line. Since the signalpropagation time is small, the signal delay time will in practice belimited by the rise time of the signal to the gate of the sourcefollower. Since the gate capacitance of the source follower is smallthis can be very fast.

Conventional methods to minimize capacitive coupling between lines havebeen to use low dielectric constant materials or insulators, or groundshields. In the present invention, it is desirable to use very lowimpedance lines it is desirable to keep the capacitive coupling betweenlines small and the magnitude of voltage steps on the interconnectionlines small. The current step will induce a voltage step at the loadwhich is the magnitude of the load impedance times this current step.This voltage step while small, 1 mA times Zin in this example, still caninduce a capacitively coupled noise signal on an adjacent line.

FIG. 3A shows an integrated circuit 300 in which a first transmissionline, strip line, or coaxial line 301A interconnects circuit components,e.g. a driver 310 to a receiver 320. FIG. 3A illustrates a firsttransmission line 301A over a conductive substrate 305. Conventionally,a voltage signal (i.e. a 5 volt signal swing) is provided by the driver310 to the transmission line 301A. The schematic illustrations in FIG.3A demonstrate that the transmission line 301A includes a smallresistance, shown generally by resistor symbols 302A, 302B, . . . ,302N. Also, the transmission line 301A includes a distributed inductance(L) which is represented generally by inductor symbols 303A, 303B, . . ., 303N. In one embodiment, the driver 310 may be an inverter 310 and thereceiver 320 may be an amplifier 320. Capacitor plate symbols 304 (C)are used to schematically represent the capacitive coupling which occursbetween the transmission line 301A and the conducting substrate 305. InFIG. 3A, a second transmission line 301B is shown. Capacitor platesymbols 306 are used to schematically represent the capacitive coupling(Cint) which similarly occurs between the first transmission line 301Aand neighboring transmission lines, e.g. second transmission line 301B.

FIG. 3B illustrates two interconnection lines in close proximity and theinterwire capacitance between these lines and the mutual inductancecoupling between the lines. (See generally, H. Johnson, “High-SpeedDigital Circuits: A Handbook of Black Magic,” Prentice-Hall, 1993; andS. Ramo, J. R. Whinnery and T. Van Duzer, “Fields and Waves inCommunication Electronics, 3rd Ed.,” John Wiley, New York, 1994).Although the interconnection lines on integrated circuits might tend tobe more square than round, the concepts involved can be mostconveniently described and formulas approximated by assuming forsimplicity that the lines are round or circular. Approximate formulashave been developed describing round wires over conductive planes or twowires in close proximity, in this case they are interconnection wires ona CMOS integrated circuit, interposer, or printed circuit board.

In FIG. 3B the illustrated pair of interconnect, or transmission lines,301A and 301B, displayed in a perspective view, are separated from aconducting substrate 305. The transmission lines, 301A and 301B arespaced a distance (h) from the conducting substrate 305 and a distance(s) from one another. The transmission lines, 301A and 301B, are shownin a circular geometry, each with a diameter (a). Some generalcharacterizations can be made about the transmission lines, 301A and301B, in an environment floating or suspended in air. First, eachtransmission line, 301A and 301B, will have a characteristic impedancein air (Z₀) approximately or generally given by Z₀≈60 ln(4 h/a). Second,each transmission line, 301A and 301B, has a inductance (L) which isL≅5.08×10⁻⁹×ln(4 h/a) Henrys/inch (H/inch). Additionally, the twotransmission lines, 301A and 30 1B, will exhibit an interwire mutualinductance (M) which is given by M=L×{1/[1+(s/h)²]}. Third, an interwirecapacitive coupling (Cint) exists between the two transmission lines,301A and 301B, and is expressed as Cint=πε/cos h⁻¹(s/a). Using thetrigonometric relationship of cos h⁻¹(y)≈ ln(2 y), the interwirecapacitive coupling can similarly be expressed as Cint≈πε/ln(2 s/a).Thus, in this environment, the two transmission lines, 301A and 301B,exhibit an interline capacitance (Cint) given by Cint={0.7/[ ln(2 s/a)]}pico Farads/inch (pF/inch). Lastly, each transmission line, 301A and301B, will further exhibit capacitive coupling C with the conductingsubstrate 305.

Again, in FIG. 3B the transmission lines, 301A and 301B, are spaced adistance (h) from the conducting substrate 305. Using the method ofimages and the interwire capacitive relationship, Cint≈πε/ln(2 s/a), asingle transmission line, 301A, over a conducting substrate is given byC≈2πε/ln(4 h/a) pF/inch where h=s/2. Thus, in this environment, the twotransmission lines, 301A and 301B, exhibit a capacitance, or capacitivecoupling C with the conductive substrate 305 which is C≈{1.41/[ ln(4h/a)]} pF/inch. The above equations have been presented by assuming thatthe transmission lines have round or circular geometries. Actualtransmission lines on integrated circuits might tend to be more squareor rectangular than round due to present lithography techniques.Nevertheless, due to the actual physical size of transmission lines,determined according to minimum lithographic feature techniques, theformulas scale well to square, rectangular or other physical crosssectional geometries for the transmission lines.

The signal rise time (trise) in conventional voltage signaling isnormally slow due to the limited ability of the transmission linedrivers to supply the large currents needed to charge these capacitancesover large voltage swings. The signal rise times are usually much largerthan the signal transmission time down the line (tprop). Additionally,if two transmission lines are in close proximity then the voltage swingon one transmission line can induce a large voltage swing or noisevoltage on the adjacent transmission line. The noise voltage isdetermined by the capacitance ratios of interwire capacitance, Cint, tothe capacitance of the transmission line with the substrate, C. In otherwords, the noise voltage is determined according to the ratio Cint/C.

The values of Cint and C can be comparable, dependant upon the insulatorthickness (h) under the transmission lines and the spacing between thetransmission lines. Emphasis in prior art is placed upon minimizing thecapacitance of the transmission line, C, by using thick insulators andlow dielectric constant materials. Emphasis is also to some extentplaced upon minimizing the interwire capacitance, Cint. Thus, theapproach in the prior art results in a noise voltage which can be alarge fraction of the signal voltage if the transmission lines are inclose proximity and far removed from the substrate by being over thickinsulators.

FIG. 4 is a perspective view illustrating a pair of neighboringtransmission lines, 401A and 401B, above a conductive substrate 405according to the teachings of the present invention. The presentinvention is designed to use current signaling across low impedancetransmission lines, 401A and 401B, to reduce signal transmission delayand to improve signaling performance over longer transmission lines.Under conventional voltage signaling the current provided in thetransmission lines is too weak to provide clean, accurately detectablecurrent signal. In order to obtain better current signals in thetransmission lines the signal to noise ratio of the transmission lines,401A and 401B, must be improved.

To improve the signal to noise ratio of the transmission lines, 401A and401B, the capacitance coupling between the transmission lines, 401A and401B, and the conductive substrate 405, is made large. Thecharacteristic impedance (Zo) of the transmission lines, 401A and 401B,can be expressed as Z₀=√{square root over (L/C)}. Thus, making C largemakes the characteristic impedance Zo=Zin, small and similarly makes thevoltage division ratio for capacitive coupling small. In the presentinvention, C increases as the insulator 407 thickness (h) separating thetransmission lines, 401A and 401B, from the ground plane, or substrate405 is decreased. In FIG. 4, the transmission lines, 401A and 401B, areseparated a distance (h) from the conducting substrate 405 by aninsulating layer 407. In one embodiment, the insulating layer 407 is anoxide layer 407. The capacitive coupling C between the transmissionlines, 401A and 401B, and the conducting substrate 405 separated by anoxide layer 407 is given as C≈1.66/[ ln(4 h/a)] pF/cm. Additionally, theinductance (L) for the transmission lines, 401A and 401B, over the oxidelayer 407 is L≈2×ln(4 h/a) nanoHenrys/centimeter (nH/cm). Thetransmission lines, 401A and 401B, are shown in a square geometry havinga width (a). The insulator 407 has a thickness (b) separating thetransmission lines, 401A and 401B from the substrate. 405. According tothe teachings of the present invention, the insulator thickness (b) ismade thinner than the thickness (t) of the transmission lines, 401A and401B. The center of the transmission lines, 401A and 401B, are adistance (h) above the conducting substrate 405. Unlike prior art wherethe emphasis is placed upon on minimizing transmission line capacitance(C), the opposite is true here where the emphasis is on minimizingcharacteristic impedance (Z₀) by making the capacitance of the lines,401A and 401B large and thus improving the signal to noise ratio.According to the teachings of the present invention, in one embodimentthe thickness (b) of the insulator is equal to or less than 1.0micrometers (μm). In one embodiment, the thickness (t) of the of thetransmission lines, 401A and 401B is equal to or greater than 1.0micrometers (μm). In one embodiment, the thickness (t) of thetransmission lines, 401A and 401B is approximately 1.0 (μm). In oneembodiment, the width (a) of the transmission lines, 401A and 401B isapproximately 1.0 micrometers (μm). As one of ordinary skill in the artwill appreciate upon reading the present disclosure, one embodiment ofthe present invention includes transmission lines 401A and 401B formedaccording to the above described dimensions and separated from thesubstrate 405 by an insulator having a thickness (b) of less than 1.0micrometers (μm). In one exemplary embodiment, the transmission lines401A and 401B have an input impedance (Z₀) approximately equal to 50ohms.

FIG. 5 is a perspective view illustrating another embodiment for a pairof neighboring transmission lines, 501A and 501B, above a conductivesubstrate 505, according to the teachings of present invention. In thisembodiment, a thickness (t) for each of the transmission lines, 501A and501B, is less than the width (a) of the transmission lines, 501A and501B. In this embodiment, the reduced thickness (t) of the transmissionlines, 501A and 501B further minimizes interwire capacitive coupling(Cint). Again, as in FIG. 5C, the insulator 507 thickness (b) over thesubstrate 505 is made small to increase the capacitive coupling Cbetween the transmission lines, 501A and 501B, and the substrate 505. Inone embodiment, the width (a) of the transmission lines, 501A and 501B,is approximately 1.0 micrometers (μm) and the thickness (b) of theinsulator layer 507 is equal to at most ¾ of the width (a) of thetransmission lines, 501A and 501B. The center of the transmission lines,501A and 501B1, are a distance (h) above the conducting substrate 505.Correspondingly, the characteristic impedance Zo of the transmissionlines, 501A and 501B, is reduced as Zo is dependent upon C. Thetransmission lines, 501A and 501B, have a low characteristic impedance(Z₀) and an improved signal to noise ratio. In one embodiment, thecharacteristic impedance Zo of the transmission lines, 501A and 501B, isapproximately 30 Ohms. The current steps produced by a driver willinduce a voltage step at the load which is the magnitude of the loadimpedance Zo times this current step. If a 1 mA current is provided tothe transmission lines, 501A and 501B, a 30 mV step results on thetransmission lines, 501A and 501B.

This embodiment, also results in a fast time constant (RC or ZoC) on thetransmission lines, 501A and 501B. In one exemplary embodiment, eachtransmission line, 501A and 501B, has a length (l) of 0.1 cm or 1000 μm,each has a width (a) of approximately 1.0 μm, h is 0.68 μm, and theinsulator layer thickness (b) is approximately 0.2 μm. In thisembodiment, the ln(4 h/a) will be approximately 1. Thus, C≈1.66/[ ln(4h/a)] pF/cm for a line of 0.1 cm will produce C≈0.2 pF. If Zo isapproximately 30 Ohms, then the time constant (ZoC) is approximately 6pico seconds (ps). Thus, the low impedance transmission lines, 501A and501B of the present invention keep the magnitude of the voltage steps onthe transmission lines, 501A and 501B, small and the response time(tprop) rapid.

As one of ordinary skill in the art will understand upon reading thisdisclosure, in both embodiments of FIGS. 4 and 5 a characteristicimpedance of 50 ohms on a given transmission line is easily realizablewhich results in a 50 mV step on one line. Thus, in the invention, thecapacitance division ratio might easily be small, C=1 pF, Cint=0.06 pF,resulting in a small noise signal on an adjacent transmission line. Thetime constant of a second, neighboring transmission line is fast, 50ohms times 1 pF, and 50 picoseconds. This means the noise current on thesecond line (Cint)×(50 mV/100 pS) or 0.03 mA. This is only a smallpercentage of the signal current and again the signal to noise ratiowill be large. It can be shown in general the signal to noise ratio dueto capacitive coupling is of the order (C/Cint) (trise/tprop); where,trise, is the rise time on the current signal and, tprop, the signalpropagation time down the line.

In summary, when transmission line effects become important onintegrated circuits interconnections at high switching speeds thenlimiting cross coupling and interconnection noise is just not simply amatter of limiting the ratio of the stray capacitance to linecapacitance, Cint/C. In other words, solely using a shielding techniqueas shown in FIG. 2 for R-C limited lines or for low impedance lines doesnot always suffice. In the present invention, capacitive couplingeffects can be minimized by:

(i) using low impedance lines and maximizing line capacitance to groundplanes as shown in FIG. 4, and

(ii) geometry, that is by making the lines wide and thin as shown inFIG. 5.

FIG. 6 is a schematic diagram for an interconnection on an integratedcircuit 600 according to the teachings of the present invention. Theinterconnection on the integrated circuit 600 includes a pair oftransmission lines, 601A and 601B, in close proximity. The firsttransmission line 601A is separated by a distance (s) from the secondtransmission line 601B. The first transmission line 601A and the secondtransmission line 601B each have a first end, 605A and 605Brespectively. In one embodiment, the first end 605A for the firsttransmission line 601A is coupled to a driver 603. The firsttransmission line 601A and the second transmission line 601B each have asecond end, 606A and 606B respectively. In one embodiment, the secondend 606A is coupled to a termination 604 formed using a complementarymetal oxide semiconductor (CMOS) process.

Reference to FIG. 6 is useful in explaining the reduced amount of noisecurrent between two transmission lines, 601A and 601B, using the currentsignaling technique of the present invention. In one embodiment of thepresent invention, transmission lines, 601A and 601B, have a lowcharacteristic impedances Zo. In one embodiment, the input impedance(Zin) seen by the driver 603 coupling to the first transmission line601A (in this example the “driven line”) is just the characteristicimpedance Zo for the first transmission line 601A. In other words, theCMOS termination 604 is impedance matched to the characteristicimpedance Zo of the transmission line 601A.

In one embodiment, the first transmission line 601A is separated byapproximately 3 μm from the second transmission line 601B and thetransmission lines have a length (l) of at least 500 μm. In anotherembodiment the transmission lines, 601A and 601B, have a length (1) ofat least 0.1 cm, or 1000 μm. As in FIGS. 4 and 5, the transmissionlines, 601A and 601B, are separated from a conducting substrate by aninsulating layer. In one embodiment, the insulating layer is an oxidelayer. In this embodiment, the capacitive coupling C between thetransmission lines, 601A and 601B, and the conducting substrate is givenas C≈1.66/[ ln(4 h/a)] pF/cm. In one exemplary embodiment, eachtransmission line, 601A and 601B, has a length (l) of 0.1 cm or 1000 μm,each has a width (a) of approximately 1.0 μm, and the insulator layerthickness (b) is approximately 0.2 μm. In this embodiment, the ln(4 h/a)will be approximately 1. Thus, C≈1.66/[ ln(4 h/a)] pF/cm and for a line0.1 cm long will produce a C≈0.2 pF. In the same embodiment, theinductance (L) for the transmission lines, 601A and 601B, over the oxidelayer is L≈2×ln(4 h/a) nH/cm, or L=0.2 nH for a line 0.1 cm long. Inthis embodiment, a 1 milli Ampere (mA) current step, i₁(t), is appliedto the gate 602 of a transistor driver 603. In one embodiment, thedriver is an n-channel source follower driver 603. In this embodiment,the rise time (trise) on the gate 602 of the driver 603 is approximately100 ps. This is the limiting time on the system response since thesignal delay (tprop) down a the transmission line is proportional to√{square root over (LC)}. For a 0.1 cm transmission line, 601A or 601B,tprop is only 7 ps. A current, di₁(t)/dt, of approximately 1×10⁷ A/secis then produced on the first transmission line 601A.

The noise current i₂(t) induced on the second transmission line 601B byinterwire capacitive coupling (Cint) is calculated as approximatelyi₂(t)=(Cint)×(V₁step/trise). The interwire capacitive coupling (Cint)between the transmission lines, 601A and 601B, separated by an oxidedielectric can be expressed as Cint=0.46 pF/cm. Again, for a 0.1 cmtransmission line, 601A or 601B, Cint≈0.05 pF. As described inconnection with FIG. 5, a 1 mA current provided to the firsttransmission line 601A having a low characteristic impedance Zo ofapproximately 30 Ohms will result in a corresponding 30 mV Voltage step(V₁step) on the first transmission line 601A. Therefore, if trise is 100ps a noise current, i₂(t), of approximately 0.015 mA is produced on thesecond, neighboring, transmission line 601B. This noise current, i₂(t),induced in the second transmission line 601B is a very small percentage,or about 1%, of the signal current i₁(t) provided to the firsttransmission line 601A. Hence, the signal to noise ratio (SNR) will belarge. It can be shown, in general, that a signal to noise ratio (SNR)for the present invention, due to capacitive coupling is of the order(C/Cint) (trise/tprop); where, trise, is the rise time for the currentsignal and, tprop, the signal propagation time down the firsttransmission line 601A. The rise time on the signal current, i₁(t), inthe first transmission line 601A is fast and just follows the rise time(trise) on the input signal, or 100 ps. The response time of this systemutilizing current signals is thus much faster than those using voltagesignals.

Reference to FIG. 6 is similarly useful to illustrate the noise voltagesignal from magnetic coupling induced in the second transmission line601B by the signal current in the first transmission line 601A. As shownin FIG. 6, a voltage will be induced in the second transmission line601B which has a magnitude that depends on the trise, di₁(t)/dt, of thecurrent i₁(t) in the driven transmission line 601A, and the mutualinductance coupling (M) between neighboring transmission lines, e.g.601A and 601B. Each transmission line, 601A and 601B, has an inductance(L). As stated above, L≈0.2 nH for a 0.1 cm transmission line, 601A and601B. In one exemplary embodiment, the current i₁(t) in the firsttransmission line, 601A (in this example the “driven line”) rises to 1mA in 100 ps. A current, di₁(t)/dt, of approximately 1×10⁷ A/sec is thenproduced on the first transmission line 601A. As presented above inconnection with FIGS. 3A and 3B, the mutual inductance coupling (M) canbe expressed as M=L×{1/[1+(s/h)²]}. In one exemplary embodiment, s isapproximately equal to 3 μm, and h is approximately equal to 0.7 μm. Inthis embodiment, M will equate to approximately M=0.02 nano Henrys (nH).

Using the relationship that the induced voltage (Vind)=M×di₁(t)/dt, Vindis approximately equal to 0.2 mV. During this 100 ps time period theinduced voltage traveling down the second transmission line 601B justsees the characteristic impedance Zo of the second transmission line601B. In one embodiment Zo is approximately 30 Ohms, so here, thecurrent induced i₂(t) in the second transmission line is i₂(t) =Vind/ Zoor 0.007 mA. This low value current is only approximately one percent(1%) of the signal current i₁(t) on the first transmission line, 601A.Hence, a large signal to noise ratio (SNR) results. In contrast, underthe prior technology, if high impedance capacitive loads had been usedon high characteristic impedance lines and conventional voltagesignaling employed there is typically a large noise voltage between theneighboring transmission lines, 601A and 601B. In the prior technology,the large noise voltage can be about one half as big as signal voltages.

The second transmission line 601B has an equivalently rapid timeconstant, (L/R) to that of the first transmission line 601A. In theembodiment presented above, the time constant is approximately 7 picoseconds (ps). The noise current i₂(t) in the second transmission line601B will reach a steady state in that time constant. The noise currentstays at this steady state value until the end of trise, in thisembodiment 100 ps, at which point i₁(t) stops changing. After this, thenoise current in the second line decays away very quickly. Again, whenthe input impedance seen by the driver 603 is matched to thecharacteristic impedance Zo of the first transmission line 601A, thesignal to noise ratio (SNR) due to inductive coupling between the firsttransmission line 601A and the second, or neighboring, transmission line601B is of the order, (L/M) (trise/tprop). In other embodiments, theactual mutual inductance and self inductances may vary from these givenvalues without departing from the scope of the invention.

FIGS. 7A-7F illustrate an embodiment of a process of fabrication oftransmission lines in an integrated circuit according to the teachingsof the present invention. The sequence of the process can be followed asa method for forming integrated circuit lines and as a method forforming transmission lines in a memory device.

FIG. 7A shows the structure after the first sequence of processing. Afirst layer of electrically conductive material 720 is formed on asubstrate 710. The first layer of electrically conductive material 720is formed on the substrate 710 by depositing a conducting film of highconductivity using a technique such as evaporation, sputtering orelectroplating. In one embodiment, the first layer of electricallyconductive material 720 is a ground plane. In an alternative embodiment,the first layer of electrically conductive material 720 is a powerplane. In a further embodiment, the first layer of electricallyconductive material 720 has a thickness (t_(CM1)) of approximately 3 to5 micrometers (μm). In further embodiments, the first layer ofelectrically conductive material 720 is coupled to a power supply or aground potential, allowing this layer to function as a direct current(DC) bus. In one embodiment, the first layer of electrically conductivematerial 720 includes copper. In another embodiment, the first layer ofelectrically conductive material 720 includes aluminum. In still anotherembodiment, the first layer of electrically conductive material 720includes any other suitably conductive material. In one embodiment, thesubstrate 710 is a bulk semiconductor (e.g., material from the Si, SiGeand GaAs family). In an alternative embodiment, the substrate 710 is aninsulator material. In another embodiment, the substrate 710 is a SOI(Silicon-On-Insulator) material.

FIG. 7B illustrates the structure following the next sequence ofprocessing. A first layer of insulating material 730 is formed on thefirst layer of electrically conductive material 720. In one embodiment,the first layer of insulating material 730 is formed by chemical vapordeposition (CVD). In one embodiment, the first layer of insulatingmaterial 730 is an oxide layer (e.g., SiO₂). In an alternativeembodiment, the first layer of insulating material 730 is an insulatorwith having a dielectric constant equivalent to or greater that adielectric constant of SiO₂. According to the teachings of the presentinvention, the first layer of insulating material 730 has a thickness(t_(IM1)) of less than 1.0 μm. FIG. 7C illustrates the structurefollowing the next sequence of processing. A pair of electricallyconductive lines 740A and 740B are formed on the first layer ofinsulating material 730. In one embodiment, the pair of electricallyconductive lines 740A and 740B have a width (W_(CL)) which isapproximately equal to 1.0 micrometers (μm). However, the invention isnot so limited. In one embodiment, the thickness (t_(CL)) of theelectrically conductive lines, 740A and 740B is equal to or less than1.0 micrometers (μm). As one of ordinary skill in the art willappreciate upon reading the present disclosure, one embodiment of thepresent invention includes electrically conductive lines 740A and 740Bformed according to the above described dimensions and separated fromthe substrate by an insulator having a thickness (b) of less than 1.0micrometers (μm). In one embodiment, the pair of electrically conductivelines 740A and 740B are formed using optical lithography followed by anadditive metallization, such as lift-off evaporation or electroplating,both of which are low-temperature processing.

FIG. 7D illustrates the structure following the next sequence ofprocessing. A transmission line 750 is formed on the first layer ofinsulating material 730. In particular, the transmission line 750 isformed between and in parallel with the pair of electrically conductivelines 740A and 740B. In one embodiment, the transmission line 750 has awidth (W_(TL)) which is approximately equal to 1.0 micrometers (μm).However, the invention is not so limited. In one embodiment, thetransmission line 750 is formed with a thickness (t_(TL)) of 1.0micrometers (μm) or less. In one embodiment, the transmission line 750is formed according to embodiments described in application Ser. No.09/247,680, entitled “Current Mode Signal Interconnects and CMOSAmplifier,” filed on Feb. 9, 1999. Similar to the processing of FIG. 7C,the transmission line 750 can be formed using optical lithographyfollowed by an additive metallization, such as lift-off evaporation orelectroplating, both of which are low-temperature processing.

FIG. 7E illustrates the structure following the next sequence ofprocessing. A second layer of insulating material 760 is formed on thepair of electrically conductive lines 740A and 740B and the transmissionline 750. In one embodiment, the second layer of insulating material 760is formed by chemical vapor deposition (CVD). In one embodiment, thesecond layer of insulating material 760 is an oxide layer (e.g., SiO₂).In an alternative embodiment, the second layer of insulating material760 is an insulator having a dielectric constant which is equivalent toor greater than SiO₂. In yet another embodiment, the second layer ofinsulating material 760 is an insulator having a dielectric constantwhich is less than that of SiO₂. In one embodiment of FIG. 7E, thesecond layer of insulating material 760 has a thickness (t_(IM2)) whichis at least 50% greater than a thickness (t_(CL)) of the pair ofelectrically conductive lines 740A and 740B and the transmission line750. Advantageously, this level of thickness insures step coverage atthe conductor corners.

FIG. 7F illustrates the structure following the next sequence ofprocessing. A second layer of electrically conductive material 770 isformed on the second layer of insulating material 760. The second layerof electrically conductive material 770 is formed on the second layer ofinsulating material 760 by depositing a conducting film of highconductivity using a technique such as evaporation, sputtering orelectroplating. In one embodiment, the second layer of electricallyconductive material 770 is a ground plane. In an alternative embodiment,the second layer of electrically conductive material 770 is a powerplane. In a further embodiment, the second layer of electricallyconductive material 770 has a thickness (t_(CM2)) of approximately 3 to5 micrometers (μm). In further embodiments, the second layer ofelectrically conductive material 770 is coupled to a power supply or aground potential, allowing this layer to function as a direct current(DC) bus. In one embodiment, the second layer of electrically conductivematerial 770 includes copper. In another embodiment, the second layer ofelectrically conductive material 770 includes aluminum. In still anotherembodiment, the second layer of electrically conductive material 770includes any other suitably conductive material.

FIGS. 8A-8F illustrate another embodiment of a process of fabrication oftransmission lines in an integrated circuit according to the teachingsof the present invention. The sequence of the process can be followed asa method for forming integrated circuit lines and as a method forforming transmission lines in a memory device.

FIG. 8A shows the structure after the first sequence of processing. Afirst layer of electrically conductive material 820 is formed on asubstrate 810. The first layer of electrically conductive material 820is formed on the substrate 810 by depositing a conducting film of highconductivity using a technique such as evaporation, sputtering orelectroplating. In one embodiment, the first layer of electricallyconductive material 820 is a ground plane. In an alternative embodiment,the first layer of electrically conductive material 820 is a powerplane. In a further embodiment, the first layer of electricallyconductive material 820 has a thickness (t_(CM1)) of approximately 3 to5 micrometers (μm). In further embodiments, the first layer ofelectrically conductive material 820 is coupled to a power supply or aground potential, allowing this layer to function as a direct current(DC) bus. In one embodiment, the first layer of electrically conductivematerial 820 includes copper. In another embodiment, the first layer ofelectrically conductive material 820 includes aluminum. In still anotherembodiment, the first layer of electrically conductive material 820includes any other suitably conductive material. In one embodiment, thesubstrate 810 is a bulk semiconductor (e.g., material from the Si, SiGeand GaAs family). In an alternative embodiment, the substrate 810 is aninsulator material. In another embodiment, the substrate 810 is a SOI(Silicon-On-Insulator) material.

FIG. 8B illustrates the structure following the next sequence ofprocessing. A first layer of insulating material 830 is formed on thefirst layer of electrically conductive material 820. In one embodiment,the first layer of insulating material 830 is formed by chemical vapordeposition (CVD). In one embodiment, the first layer of insulatingmaterial 830 is an oxide layer (e.g., SiO₂). In an alternativeembodiment, the first layer of insulating material 830 is an insulatorhaving a dielectric constant which is equivalent to or greater thanSiO₂. According to the teachings of the present invention, the firstlayer of insulating material 830 has a thickness (t_(IM1)) of less than1 μm.

FIG. 8C illustrates the structure following the next sequence ofprocessing. A pair of electrically conductive lines 840A and 840B areformed on the first layer of insulating material 830. In one embodiment,the pair of electrically conductive lines 840A and 840B have a width(W_(CL)) which is approximately equal to 1.0 micrometers (μm). However,the invention is not so limited. In one embodiment, the width (W_(CL))of the electrically conductive lines, 840A and 840B is approximately 1.0micrometers (μm). As one of ordinary skill in the art will appreciateupon reading the present disclosure, one embodiment of the presentinvention includes electrically conductive lines 840A and 840B formedaccording to the above described dimensions and separated from thesubstrate by an insulator having a thickness (b) of less than 1.0micrometers (μm). In one embodiment, the pair of electrically conductivelines 840A and 840B are formed using optical lithography followed by anadditive metallization, such as lift-off evaporation or electroplating,both of which are low-temperature processing.

FIG. 8D illustrates the structure following the next sequence ofprocessing. A pair of transmission lines 850A and 850B are formed on thefirst layer of insulating material 830. In particular, the pair oftransmission lines 850A and 850B are formed between and parallel withthe pair of electrically conductive lines 840A and 840B. In oneembodiment, the pair of transmission lines 850A and 850B have a width(W_(TL)) which is approximately equal to 1.0 micrometers (μm). However,the invention is not so limited. In one embodiment, the pair oftransmission lines 850A and 850B are formed with a thickness (t_(TL))equal to 1.0 micrometers (μm) or less. In one embodiment, the pair oftransmission lines 850A and 850B are formed according to embodimentsdescribed in application Ser. No. 09/247,680, entitled “Current ModeSignal Interconnects and CMOS Amplifier,” filed on Feb. 9, 1999. Similarto the processing of FIG. 8C, the pair of transmission lines 850A and850B can be formed using optical lithography followed by an additivemetallization, such as lift-off evaporation or electroplating, both ofwhich are low-temperature processing.

FIG. 8E illustrates the structure following the next sequence ofprocessing. A second layer of insulating material 860 is formed on thepair of electrically conductive lines 840A and 840B and the pair oftransmission lines 850A and 850B. In one embodiment, the second layer ofinsulating material 860 is formed by chemical vapor deposition (CVD). Inone embodiment, the second layer of insulating material 860 is an oxidelayer (e.g., SiO₂). In an alternative embodiment, the second layer ofinsulating material 860 is an insulator having a dielectric constantwhich is equivalent to or greater than SiO₂. In yet another embodiment,the second layer of insulating material 860 is an insulator having adielectric constant which is less than that of SiO₂. In one embodimentof FIG. 8E, the second layer of insulating material 860 has a thickness(t_(IM2)) which is at least 50% greater than a thickness (t_(CL)) of thepair of electrically conductive lines 840A and 840B and the pair oftransmission lines 850A and 850B. Advantageously, this level ofthickness insures step coverage at the conductor corners.

FIG. 8F illustrates the structure following the next sequence ofprocessing. A second layer of electrically conductive material 870 isformed on the second layer of insulating material 860. The second layerof electrically conductive material 870 is formed on the second layer ofinsulating material 860 by depositing a conducting film of highconductivity using a technique such as evaporation, sputtering orelectroplating. In one embodiment, the second layer of electricallyconductive material 870 is a ground plane. In an alternative embodiment,the second layer of electrically conductive material 870 is a powerplane. In a further embodiment, the second layer of electricallyconductive material 870 has a thickness (t_(CM2)) of approximately 3 to5 micrometers (μm). In further embodiments, the second layer ofelectrically conductive material 870 is coupled to a power supply or aground potential, allowing this layer to function as a direct current(DC) bus. In one embodiment, the second layer of electrically conductivematerial 870 includes copper. In another embodiment, the second layer ofelectrically conductive material 870 includes aluminum. In still anotherembodiment, the second layer of electrically conductive material 870includes any other suitably conductive material.

FIG. 9 is a block diagram which illustrates an embodiment of a system900 using line signaling according to teachings of the presentinvention. The system 900 includes a low output impedance driver 910having a driver impedance, as is well known in the art. The low outputimpedance driver 910 is coupled to a transmission line circuit 920.Embodiments of the transmission line circuit 920 are described andpresented above with reference to FIGS. 3-8. Moreover, the system 900includes a termination circuit 930 having a termination impedance thatis matched to the impedance of the transmission line circuit 920.

FIG. 10 is a block diagram which illustrates an embodiment of a system1000 according to teaching of the present invention. The system 1000includes an integrated circuit 1010. The integrated circuit 1010includes the transmission line circuit described and presented abovewith reference to FIGS. 3-8. Additionally, the system 1000 includes aprocessor 1020 that is operatively coupled to the integrated circuit1010. The processor 1020 is coupled to the integrated circuit 1010through a system bus 1030. In one embodiment, the processor 1020 and theintegrated circuit 1010 are on the same semiconductor chip.

Conclusion

Thus, improved methods and structures are provided using capacitivetechniques to reduce noise in high speed interconnections, such as thoseused in CMOS integrated circuits. The present invention also offers areduction in signal delay. Moreover, the present invention furtherprovides a reduction in skew and crosstalk. Embodiments of the presentinvention also provide the fabrication of improved transmission linesfor silicon-based integrated circuits using conventional CMOSfabrication techniques.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. It is to be understood that the above description is intendedto be illustrative, and not restrictive. Combinations of the aboveembodiments, and other embodiments will be apparent to those of skill inthe art upon reviewing the above description. The scope of the inventionincludes any other applications in which the above structures andfabrication methods are used. The scope of the invention should bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

1. A memory comprising: a bottom plane of electrically conductivematerial disposed on a substrate; a layer of a insulating materialdisposed on the bottom plane, the layer of insulating material having athickness of less than 1.0 micrometer (μm); and a transmission linedisposed on the layer of insulating material.
 2. The memory of claim 1,wherein the transmission line has a thickness equal to the thickness ofthe layer of insulating material.
 3. The memory of claim 1, wherein thetransmission line has a thickness greater than the thickness of thelayer of insulating material.
 4. The memory of claim 3, wherein thetransmission line has a width such that its thickness substantiallyequals its width.
 5. The memory of claim 1, wherein the transmissionline has a thickness and a width such that the thickness is less thanthe width.
 6. The memory of claim 1, wherein the transmission line has awidth of approximately 1.0 micrometers such that the thickness of theinsulating layer is at most three-fourths of the width.
 7. The memory ofclaim 1, wherein the memory includes a conductive plane disposed abovethe transmission line.
 8. The memory of claim 7, wherein the conductiveplane includes a power plane.
 9. The memory of claim 1, wherein thememory includes a dielectric disposed on and contacting the transmissionline, the dielectric material having a dielectric constant differentfrom that of silicon oxide.
 10. The memory of claim 1, wherein thememory includes another transmission line such that the transmissionlines are capacitively coupled to each other and are separated from eachother by approximately 3.0 μm, each transmission line having a length ofat least 50 μm.
 11. A memory comprising: a bottom ground plane formed ona substrate; a layer of insulating material formed on the bottom groundplane, wherein the layer of insulating material has a thickness of lessthan 1.0 micrometers (μm); a pair of electrically conductive linesformed on the layer of insulating material; a pair of differentialsignal lines formed on the layer of insulating material, the pair ofdifferential signal lines between and parallel with the pair ofelectrically conductive lines; and a top ground plane formed above thelayer of insulating material.
 12. The memory of claim 11, wherein thebottom and top ground planes have a thickness of approximately 3 to 5micrometers (μm).
 13. The memory of claim 11, wherein the top and bottomground planes include copper.
 14. The memory of claim 11, wherein thepair of electrically conductive lines and the pair of differentialsignal lines have a width and a thickness of approximately 1.0 μm. 15.The memory of claim 11, wherein the pair of electrically conductivelines and the pair of differential signal lines have a thickness of lessthan 1.0 μm.
 16. The memory of claim 11, wherein a first end of each ofthe pair of differential signal lines is coupled to a low outputimpedance driver having a driver impedance and wherein a second end ofeach of the pair of differential signal lines is coupled to atermination circuit having a termination impedance that is matched tothe driver impedance.
 17. The memory of claim 11, wherein the substrateincludes a bulk semiconductor.
 18. The memory of claim 11, wherein thedifferential signal lines are configured in a differential line circuitin a dynamic random access memory (DRAM).
 19. A memory comprising: abottom ground plane disposed on a substrate; a first layer of a firstinsulating material disposed on the bottom ground plane, the first layerof the first insulating material having a thickness of less than 1.0micrometer (μm); a pair of electrically conductive lines disposed on thefirst layer of the first insulating material; a transmission linedisposed on the first layer of the first insulating material, thetransmission line arranged between and parallel with the pair ofelectrically conductive lines; and a second layer of a second insulatingmaterial disposed on the electrically conductive lines and on thetransmission line.
 20. The memory of claim 19, wherein the bottom groundplane includes a metal ground plane.
 21. The memory of claim 19, whereinthe first insulating material and the second insulating material have acommon composition.
 22. The memory of claim 19, wherein the secondinsulating material has a composition having a dielectric constantdifferent from that of the first insulating material.
 23. The memory ofclaim 22, wherein the first insulating material is silicon oxide. 24.The memory of claim 19, wherein the transmission line has a thicknessand each of the electrically conductive lines has a thickness such thatthe transmission line and the pair of electrically conductive lines havesubstantially the same thickness and the second insulating material hasa thickness equal to or greater than 50% larger than the thickness ofthe transmission line.
 25. The memory of claim 19, wherein thetransmission line has a width and a thickness of approximately 1.0 μm.26. The memory of claim 19, wherein the electrically conductive lineshave a width of approximately 1.0 μm and a thickness equal to or lessthan 1.0 μm.
 27. The memory of claim 19, wherein the substrate includesa SiGe-based substrate.
 28. The memory of claim 19, wherein thesubstrate includes a GaAs-based substrate.